A Charge Recycling Three-phase Dual-rail Pre-charge Logic Based Flip-flop

Providing resistance against side channel attacks especially differential power analysis (DPA) attacks, which aim at disclosing the secret key of cryptographic algorithm is one of the biggest challenges of designers of cryptographic devices. In this paper design of novel data flip-flop compatible with three-phase dual-rail logic (TDPL), called Charge recycling TDPL flip-flop is investigated. The new flip-flop uses inverters that uses the charge recycling technique where charge stored on high output node during evaluation phase is used to partially charge the low output node in subsequent pre-charge phases. As a result less charge comes from the power supply thus lowering the power consumption. Simulation results in Cadence Virtuoso 45 nm CMOS process show improvement in power consumption in inverter up to 60% while CRTDPL flip-flop consumes around 50% less power compared to TDPL flip-flop.